The present disclosure relates generally to cache coherence and, more particularly, to cache coherence between heterogeneous processors.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Multi-processor systems frequently employ cache coherence techniques to maintain the integrity of memory shared by the processors. Common cache coherence techniques may involve bus snooping, in which the processors may broadcast memory references to each other before accessing memory potentially in use by another processor. Although these cache coherence techniques may produce acceptable results with small numbers of homogenous processors with the same or similar processing capabilities and/or characteristic memory usage rates, when applied to heterogeneous processors with different processing capabilities and/or characteristic memory usage rates, excessive snoop traffic may result. Indeed, using such current techniques with a central processing unit (CPU) and a graphics processing unit (GPU), snoop traffic may bottleneck performance by consuming significant amounts of inter-processor communication bandwidth.
Alternative techniques have been developed to in an attempt to achieve memory coherence between heterogeneous processors. These techniques may involve designating exclusive pools of memory at the application level, which may result in effective cache coherence only if applications conform to such techniques. However, to employ these techniques, the applications may be required to “know” which pools of memory are allocated to which device. Since these techniques may require dramatic changes to the manner in which applications are currently written, it is unlikely that application developers will write software that efficiently maintains cache coherence according to these techniques.